--==========================================================
-- Design units : Bit_Add_G_P(entity, architecture,configuration)
--
-- File name    : CLA_1_Bit_Add_G_P.vhd
--
-- Purpose      : One bit adder with carry generate and propagate
--                               
-- Limitations  : -
--
-- Library      : IEEE
--
-- Dependencies : ELEMpack
--
-- Author       : Claus-Juergen Thomas, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- v1.0    cjt    19.12.95       new
--=========================================================
-------------------------------------------------------------------
-- Equations FOR an one bit adder with carry propagate AND GENERATE
-- G = A AND B
-- P = A OR B
-- S = ((NOT G) AND P) XOR C)
-------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ELEMpack.all;
USE work.CarryLookaheadPackage.all;

ENTITY Bit_Add_G_P IS
  PORT(A_In  : IN std_logic;      -- First summand
       B_In  : IN std_logic;      -- Second summand
       C_In  : IN std_logic;      -- Carry IN
       S_Out : OUT std_logic;     -- Sum OUT
       G_Out : OUT std_logic;     -- Carry GENERATE OUT
       P_Out : OUT std_logic);    -- Carry propagate OUT
END Bit_Add_G_P;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF Bit_Add_G_P IS

  SIGNAL internal, propagate, gen, not_gen: std_logic;

  BEGIN

    And_Gate_1: AND2
      PORT MAP(A_IN,
               B_IN,
               gen);

    Or_Gate: OR_2
      PORT MAP(A_IN,
               B_IN,
               propagate);

    Inverter: INV
      PORT MAP(gen,
               not_gen);

    And_Gate_2: AND2
      PORT MAP(not_gen,
               propagate,
               internal);

    X_or_Gate: XOR2
      PORT MAP(internal,
               C_IN,
               S_Out);

    P_Out <= propagate;
    G_Out <= gen;

END Structure;

--============================CONFIGURATION=================

CONFIGURATION Bit_Add_G_P_Config OF Bit_Add_G_P IS

  FOR Structure

    FOR all : AND2
      USE ENTITY work.AND2(Behavior);
    END FOR;

    FOR Or_Gate: OR_2
      USE ENTITY work.OR_2(Behavior);
    END FOR;

    FOR Inverter: INV
      USE ENTITY work.INV(Behavior);
    END FOR;

    FOR X_or_Gate: XOR2
      USE ENTITY work.XOR2(Behavior);
    END FOR;

  END FOR;

END Bit_Add_G_P_Config;