--==========================================================
-- Design units : MATRIXcell
--                (entity, architecture and configuration)
--
-- File name    : MATRIXcell.vhd
--
-- Purpose      : cell for 2 dim systolic array
--
-- Limitations  : none
--
-- Library      : WORK
--
-- Dependencies : IEEE,MATRIXcra,ELEMpack,MULTpack
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a on SUN SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    03.04.95       ESA standard
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.MATRIXpack.ALL;
USE work.ELEMpack.ALL;

ENTITY MATRIXcell IS
  GENERIC (M : Positive := 4;  -- input vector length
           N : Positive := 8); -- output vector length
  PORT(A_In : IN std_logic_vector(M-1 DOWNTO 0); -- input A 
       B_In : IN std_logic_vector(M-1 DOWNTO 0); -- input B
       C_In : IN std_logic_vector(N-1 DOWNTO 0); -- input C
       Reset_N : IN std_logic; -- asynchronuous reset on active low
       clock   : IN std_logic; -- clock input
       A_Out : OUT std_logic_vector(M-1 DOWNTO 0); -- stream A out
       B_Out : OUT std_logic_vector(M-1 DOWNTO 0); -- stream B out
       C_Out : OUT std_logic_vector(N-1 DOWNTO 0));-- stream C out
END MATRIXcell;

--============================ARCHITECTURE==================

ARCHITECTURE Structure OF MATRIXcell IS
  SIGNAL product : std_logic_vector((2*M)-1 DOWNTO 0);
  SIGNAL sum : std_logic_vector(N-1 DOWNTO 0);
  SIGNAL VDD,GND : std_logic;
BEGIN

  VDD <= '1';
  GND <= '0';

  reg_A : nREGr
    GENERIC MAP(M)
    PORT MAP(CLK => clock,
               S => VDD,
               R => Reset_N,
               X => A_In,
               Y => A_Out);

  reg_B : nREGr
    GENERIC MAP(M)
    PORT MAP(CLK => clock,
               S => VDD,
               R => Reset_N,
               X => B_In,
               Y => B_Out);

  mult : MULTstruc
    GENERIC MAP(M)
    PORT MAP(A => A_In,
             B => B_In,
             P => product);

  add : CRA
    GENERIC MAP(N)
    PORT MAP(A    => C_In,
             B    => product,
             Cin  => GND,
             Sum  => sum,
             Cout => OPEN);

  reg_C : nREGr
    GENERIC MAP(N)
    PORT MAP(CLK => clock,
               S => VDD,
               R => Reset_N,
               X => sum,
               Y => C_Out);

END Structure;

--============================CONFIGURATION=================

CONFIGURATION MATRIXcell_Config OF MATRIXcell IS
  FOR Structure
    FOR ALL : nREGr
      USE ENTITY work.nREGr(Structure);
    END FOR;
    FOR mult : MULTstruc
      USE ENTITY work.MULTstruc(Structure);
    END FOR;
    FOR add : CRA 
      USE ENTITY work.CRA(Structure);
    END FOR;
  END FOR;
END MATRIXcell_Config;