--==========================================================
-- Design units : FILTERpack (package)
--
-- File name    : FILTERpack.vhd
--
-- Purpose      : Summary of sturctures for systolic filter
--                benchmark
--
-- Limitations  : none
--
-- Library      : WORK
--
-- Dependencies : IEEE
--
-- Author       : Hans-Peter Eich, REFT
--
-- Simulator    : Synopsys V3.1a ON Sun SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date           Changes
--
-- V1.0    hpe    17.01.95       ESA standard
-- V1.1    cjt    03.07.95       
--=========================================================

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE FILTERpack IS
 
COMPONENT FILTERbehave
  GENERIC (N: Positive := 12;     -- n bit output stream     
           M: Positive := 4;      -- m bit input stream
           K: Positive := 3);     -- number of weight data
  PORT (StreamIn:  IN Integer RANGE (2**M)-1 DOWNTO 0;  -- Inputvector in
        CLK: IN std_logic;       -- clock in
        SelWgtStr: IN std_logic; -- select weight stream
        StoreWgt: IN std_logic;  -- store weight
        StoreStr: IN std_logic;  -- store stream
        Reset_N : IN std_logic;  -- asynchronous reset active low
        ResultOut: OUT Integer RANGE (2**N)-1 DOWNTO 0); -- Resultvector out
END COMPONENT;

COMPONENT FILTERstruc
  GENERIC(N: Positive := 12;                            -- n bit output stream
          M: Positive := 4;                             -- m bit output stream
          K: Positive := 3);                            -- number of stages
  PORT (StreamIn: IN std_logic_vector (M-1 DOWNTO 0);   -- input stream
        SelectWgtStr: IN std_logic; -- select weight stream
        StoreWgt: IN std_logic;     -- store weight
        StoreStr: IN std_logic;     -- store stream
        StoreRes: IN std_logic;     -- store result
        clk1: IN std_logic;         -- clock 1 in
        clk2: IN std_logic;         -- clock 2 in
        Reset_N: IN std_logic;      -- asynchronous reset active low
        ResultOut: OUT std_logic_vector(N-1 DOWNTO 0)); -- result stream out
END COMPONENT;

COMPONENT FILTERstage
  GENERIC (N: Positive := 12;  -- n bit output stream 
           M: Positive := 4);  -- m bit input stream
  PORT (StreamIn: IN std_logic_vector(M-1 DOWNTO 0);  -- input stream in
        ResultIn: IN std_logic_vector(N-1 DOWNTO 0);  -- result stream out
        SelectWgtStr: IN std_logic;   -- select weight stream
        StoreWgt: IN std_logic;       -- store weigth
        StoreStr: IN std_logic;       -- store stream
        StoreRes: IN std_logic;       -- store  result
        clk1: IN std_logic;           -- clock 1 in
        clk2: IN std_logic;           -- clock 2 in
        Reset_N: IN std_logic;        -- asynchronous reset active low
        StreamOut: OUT std_logic_vector(M-1 DOWNTO 0);  -- input stream out
        ResultOut: OUT std_logic_vector(N-1 DOWNTO 0)); -- result stream out
END COMPONENT;

COMPONENT MULTstruc
  GENERIC (N: Positive := 4);                           -- default n = 4
  PORT (A: IN  std_logic_vector(N-1 DOWNTO 0);          -- n bit data in
        B: IN  std_logic_vector(N-1 DOWNTO 0);          -- n bit data in
        P: OUT std_logic_vector((2*N)-1 DOWNTO 0));     -- 2*n bit data out
END COMPONENT;

COMPONENT FILTERcra
  GENERIC(N: Positive := 12;                    -- n bit
          M: Positive := 4);                    -- m bit
  PORT(A: IN  std_logic_vector(N-1 DOWNTO 0);   -- n bit data in
       B: IN  std_logic_vector(M-1 DOWNTO 0);   -- m bit data in
       S: OUT std_logic_vector(N-1 DOWNTO 0));  -- n bit sum out
END COMPONENT;

COMPONENT expand
  GENERIC(N: Positive := 8;                     -- default n = 8
          M: Positive := 4);                    -- default m = 4
  PORT(X: IN  std_logic_vector(M-1 DOWNTO 0);   -- m bit data in
       Y: OUT std_logic_vector(N-1 DOWNTO 0));  -- n bit data in
END COMPONENT;

END FILTERpack;