This directory contains two subdirectories:

  mvp_v11	a VHDL prettyfier and printout tool
                (c) 1995 M. Gumm University of Stuttgart

  vlsi_course	the complete material and source files for the
  		VLSI Design Course
                (c) 1995 M. Gumm    University of Stuttgart
		    1997 M. Buehler University of Stuttgart
                + VHDL-Models of the DLXS Prozessor 
                 	- behavioural
                 	- for synthesis
                + Documentation
                + special DLXS-assembler 
  DLXS-P.beta	a beta version of our pipelined DLXS-model
		please read 00README in directory

  iscas.tgz	the iscas benchmark set in synthesizable VHDL
		together with a converter in PERL
                	
          

 ______________________________________________________________________
/                                                                      \
|   Markus Buehler                                                     |
|                                            __  ____   _   __  ____   |
|   Integrated Systems Engineering          / / / __ \ | | / / / __ \  |
|   Institute of Parallel and Distributed  / / / /_/ / | |/ / / /_/ /  |
|   High-Performance Systems (IPVR)       / / / ____/  | | / / _  _/   |
|   University of Stuttgart              /_/ /_/       |__/ /_/ \_\    |
|                                                                      |
|   Breitwiesenstrasse 20-22                                           |
|   70565 Stuttgart                                                    |
|   Germany                                                            |
|----------------------------------------------------------------------|
|   Tel.  : ++49 (0)711 7816 396                                       |
|   Fax   : ++49 (0)711 7816 250                                       |
|   e-mail: buehlems@informatik.uni-stuttgart.de                       |
\______________________________________________________________________/