Information about VITAL

VHDL Initiative Toward ASIC Libraries

Model Development Specification

The objectives of the VITAL initiative can be summed up in one sentence:
"Accelerate the development of sign-off quality ASIC macrocell simulation libraries written in VHDL by leveraging existing methodologies of model development".

This specification is targeted toward VHDL logic simulation modeling of ASIC cells at a level of accuracy sufficient for sign-off. The techniques employed in this specification could be readily applied toward the broader segment of VHDL modeling including FPGA, standard component models and systems.

More information about VITAL can be found on the VITAL home page. NEW

VITAL ASIC Modeling Specification, Draft October 1995 (Format: PostScript)

The VITAL specification is under the supervision of the IEEE Timing Working Group, PAR 1076.4.

VITAL Packages

VITAL_Timing: A package containing data types and subprograms to support development of macrocell timing models. Included in this package are routines for delay selection, timing violation checking and reporting, and glitch detection.

VITAL.VITAL_Timing Package Header
VITAL.VITAL_Timing Package Body

VITAL_Primitive: A set of commonly used combinatorial primitives are defined in this package. The primitives are provided both in Function and concurrent Procedure form to support either behavioral or structural modelling styles. The procedure primitives support separate pin-to-pin delay path and well as GlitchOnEvent glitch detection. In addition, this package contains general purpose Truth and State Tables.

VITAL.VITAL_Primitives Package Header
VITAL.VITAL_Primitives Package Body

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Sandi Alexander Habinc (sandi@ws.estec.esa.nl)

Last edited 21 November 1996

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