the hardware interface
the interrupts management
the time management
the ATAC memory
the priority management
the ATAC clock
The ATAC coprocessor is seen by the main processor (whichever is selected) as a memory location. Each instruction of the ATAC instruction set is actually a memory address. The necessary data to perform the instruction is exchanged on the data bus.
The 32 bit hardware protocol includes a 16 bit mode. ATAC can be interfaced to either a 32bit or a 16 bit microprocessor. It has actually been interfaced to the 16 bit MA31750, an implementation of the MIL-STD-1750A/B. It is now part of the ESA SPARC ERC32 architecture.
In a hardware architecture without ATAC, the interrupt lines are connected directly to the CPU. This means that, whatever happens, the CPU has to be interrupted to consider the event. In an ATAC architecture, interrupts are no longer connected to the CPU, but to the ATAC (16 incoming lines). One single interrupt line is connected from the ATAC to the CPU, and its sole purpose is to enforce pre-emption. In this way, higher priority tasks will never be disturbed by interrupts going to lower priority tasks as is the case in traditional systems.
Not only is the priority inversion problem avoided in this situation, but also CPU execution time is saved. This part of interrupt handling, in any case performed by the CPU with a software run-time system, consumes a lot of its own time budget. Now this function is performed concurrently by ATAC.
However, interrupts can also be connected directly to the CPU. In this case, it is still possible to use the interrupt entry call mechanism, but if so, it is called explicitly from the software interrupt handler.
Time is internally maintained in ATAC, in particular for the delay and delay_until instructions and the calendar.clock function. Time is expressed as a 64 bit linear time word, with a programmable resolution down to 125 nanoseconds.
In an architecture without ATAC, external timers are needed, interrupting the CPU when the related delay expires. The CPU must then handle the interrupts, maybe refresh software clocks, consider the queues and the priorities and reschedule the tasks if necessary. High priority tasks may suffer from this. All these functions are now performed concurrently inside ATAC, keeping priority integrity and again saving CPU time.
The ATAC device includes some on-chip memory (2 Kbytes). The memory can also be extended with external memory. The external memory is fully private to ATAC and does not consume CPU address range. This allows the handling of an average of 32 tasks with no external memory, and a maximum of 2048 tasks using external memory.
The ATAC memory contains data that can be removed from the run-time system memory area, as it is always possible to ask ATAC for their value.
The priority range includes 64 levels. A large range of priority offers more flexibility to handle dynamic priority. A special setup makes ATAC run the Basic Priority Inheritance protocol (BPI). If so, ATAC raises the priority of the servers to the highest priority of the clients that are accessing them at a given moment.
The CPU and the ATAC clocks have to originate from the same source. But it is possible, for example, to run the CPU at 20 MHz and ATAC at 40 MHz. The higher the ATAC clock, the faster its answer, the lower the border of ATAC response time, the better the accuracy.
Return to the ATAC page.
Last edited 28 November 1995
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