entity MISR_Verification is
end MISR_Verification;

library IEEE;
use IEEE.Std_Logic_1164.all;

use Work.MISR_Definition.MISR;
use Work.MISR_Definition1.MISR;
 
architecture Behavioural of MISR_Verification is
   signal Clk:    Std_Logic := '0';
   signal Reset:  Boolean   := False;

   signal Input:  Std_Logic_Vector(0 to 39) := (4=>'1', others=>'0');
   signal MISR0:  Std_Logic_Vector(0 to 39);
   signal MISR1:  Std_Logic_Vector(0 to 3);
   signal MISR2:  Std_Logic_Vector(0 to 4);
   signal Input2: Std_Logic_Vector(0 to 4) := "UX01X";
   signal Input3: Std_Logic_Vector(0 to 9) := (1=>'1', 7=>'1', others=>'0');
   signal MISR3:  Std_Logic_Vector(0 to 9);

   signal Input4:  Std_Logic_Vector(0 to 9);
   signal Input4r: Std_Logic_Vector(9 downto 0);
   signal MISR4:   Std_Logic_Vector(0 to 9);
   signal MISR4r:  Std_Logic_Vector(9 downto 0);
   signal MISR41:  Std_Logic_Vector(0 to 9);
 
begin
   Reset <= True    after 250 ns,
            False   after 251 ns,
            True    after 449 ns,
            False   after 451 ns,
            True    after 652 ns,
            False   after 653 ns,
            True    after 849 ns,
            False   after 850 ns;

   Clk   <= not Clk after 50 ns;
 
   process(Clk)
   begin 
      if Rising_Edge(Clk) then
         Input <= Input(1 to 39)&Input(0) after 20 ns;
      end if;
   end process;

   process(Clk)
   begin
      if Rising_Edge(Clk) then
         Input3(0 to 3) <= Input3(1 to 3)&Input3(0) after 15 ns;
      end if;
   end process;

   process(Clk)
   begin
      if Rising_Edge(Clk) then
         Input3(6 to 9) <= Input3(7 to 9)&Input3(6) after 15 ns;
      end if;
   end process;

   Input3(5) <= not Input3(6);
   Input3(4) <= not Input3(5);

   Input4    <= Input(0 to 9);
   Input4r   <= Input(0 to 9);


   process (Clk)
   begin
      assert Input4 = Input4r report "INPUT";
      assert MISR4  = MISR4r  report "MISR4 and MISR4r";
      assert MISR4  = MISR41  report "MISR4 and MISR41";
   end process;

   Work.MISR_Definition.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input,
      MISR    => MISR0,
      Sense   => 10 ns);

   Work.MISR_Definition.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input(0 to 3),
      MISR    => MISR1,
      Rising  => True,
      Falling => True,
      Sense   => 10 ns);

   Work.MISR_Definition.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input2,
      MISR    => MISR2,
      Rising  => False,
      Falling => True,
      Sense   => 10 ns);

   AsynchronousMISR: Work.MISR_Definition.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input3,
      MISR    => MISR3,
      Rising  => False,
      Falling => False,
      Sense   => 10 ns);

   MISR_4:  Work.MISR_Definition.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input4,
      MISR    => MISR4,
      Rising  => False,
      Falling => True,
      Sense   => 10 ns,
      HeaderMsg => "MISR_4");
 
   MISR_4r:  Work.MISR_Definition.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input4r,
      MISR    => MISR4r,
      Rising  => False,
      Falling => True,
      Sense   => 10 ns,
      HeaderMsg => "MISR_4r");
 
   MISR_41:  Work.MISR_Definition1.MISR(
      Clk     => Clk,
      Reset   => Reset,
      Input   => Input4,
      MISR    => MISR41,
      Rising  => False,
      Falling => True,
      Sense   => 10 ns,
      HeaderMsg => "MISR_41");

end Behavioural;