VHDL Simulation #4, DUE Thurs, Jul 16, 6:00 pm

Matrix Multiply using Synposys Behavioral Compiler , 6:00 pm


Problem Statement

You are to create a VHDL computation block that performs a [1x4] X [4x4] matrix multiplication to produce a [1x4] matrix output. The entity declaration is: 


use work.coordxform_defs.all;
entity coordxform is

 port (
  din: in signed(INWIDTH-1 downto 0);
  clk: in std_logic;
  reset: in std_logic;
  input_rdy : out std_logic;     -- ready for new [1x4] coordinate matrix
  tmatrix_rdy : out std_logic;   -- ready for a new transformation matrix
  output_rdy : out std_logic;    -- 
  dout: out signed(OUTWIDTH-1 downto 0)
);
end coordxform;
A VHDL package called coordxform_defs will define three constants: 

package  coordxform_defs is

constant INWIDTH : integer := 14;
constant INTERNALWIDTH : integer := 16;
constant OUTWIDTH   : integer := 14;

end coordxform_defs;

The INTERNALWIDTH constant determines the precision that all internal numbers are kept in. INTERNALWIDTH will always be greater or equal to OUTWIDTH which will always be greater or equal to INWIDTH.

Operation

The contents of the 4X4 matrix will be known as the transformation matrix and will be loaded after reset into the chip. The 4x4 transformation matrix will loaded in ROW/COLUMN order: 

      T00 T01 T02 T03
      T10 T11 T12 T13
      T20 T21 T22 T23
      T30 T31 T32 T33

The tmatrix_rdy handshaking signal is used to load each element of the matrix (T00, T01, T02, T03, T10, T11, etc..). After the transformation matrix is ready, the chip should go into an infinite loop processing the 'din' input stream. Groupings of four values from the 'din' stream will be the elements of the coordinate matrix. If I have coordinates A, B, C (each represented by 4 numbers), then the 'din' input stream would be: 

 A00,A01,A02,A03,B00,B01,B02,B03,C00, etc.

The 'dout' output stream should represent the 'transformed' coordinates as represented by the result of multiplying the [1x4] x [4x4] matrices. If the transformated coordinates of A, B, C are A', B', C', then the dout output stream would contain: 

 A'00,A'01,A'02,A'03,B'00,B'01,B'02,B'03,C'00, etc.
where 
 A'00 = A00*T00 + A01*T10 + A02*T20 + A03*T30
 A'01 = A00*T01 + A01*T11 + A02*T21 + A03*T31
etc..
The input_rdy handshaking signal should be used to indicate that a new 'din' value is requested. The output_rdy handshaking signal should be used to indicate that a new 'dout' value is ready.

Requirements

  1. Create a behavioral model of coordxform and verify its operation via a VHDL testbench.
  2. Create the following implementations of coordxform using Synopsys behavioral compiler:
    1. A minimum area implementation
    2. A maximum throughput implementation (initiation rate = 1)

    For these implementations use INWIDTH=OUTWIDTH=12 bits, INTERNALWIDTH=14 bits. You must verify that the results of your implementations match that of your behavioral model.

Use the same naming convention as discussed in classed for naming your designs. They should be called coordxform_sN_iN_rN_lN_pN where:

Use synthesis scripts similar to those used for the 'summer' example discussed in class.