Dynamic Logic Homework (DUE 9/24)

Objective

To introduce the student to some issues in dynamic logic.

Problem Statement

Refer to Figure 4.73, on page 261 of the Rabaey book. For all spice simulations, use the 'nominal.bsim' model used in previous homeworks. For all input waveforms, use 0.05 ns rise,fall times; Vdd = 3.3v. For dynamic circuits, assume that all inputs change during the precharge of the clock cycle. For the source/drain areas and perimeters, use the following approximations: AD=AS = W * 3U, PD = PS = W + 6U. All numbers on the diagram are in microns. Assume that you have all inputs and their complements available.

You must define the network of figure 4.73 as a subcircuit contained in a seperate spice file. You must use names of A0, A0_B,B0, B0_B, A1, A1_B,B1, B1_B, PHI, PHI_B (if needed), G. Here A0_B is the complement of 'A0'.

Part #1

For the reference circuit, do Parts (a) & (b) of problem 20 on page 260,261. Your subcircuit must be contained in a separate spice file file called "gatedom_a.sp".

Part #2

For the reference circuit, do all Part (a) of Problem #21. Your subcircuit must be contained in a separate spice file file called "gatedom_b.sp".

Part #3

Implement the circuit as NP-CMOS. Verify its correct operation. Your subcircuit must be contained in a separate spice file file called "gatenp.sp".

Part #4

Implement the circuit as CPL-Logic. Verify its correct operation. Your subcircuit must be contained in a separate spice file file called "gatecpl.sp".

Submissions

Make a directory called 'sim3'. Put your four subcircuit files in this directory. From the directory above the 'sim3' directory, do:

  ~reese/bin/submit_ee8273_sim3.pl

This will create a compressed tar file of the hw4 directory and email it to me. This will only work from the ERC machines.

You will need to turn in hardcopy of your other results. I want to see a drawn schematics of the gates used in Parts 2,3,4.

Last modified: Thu Sep 24 16:33:28 CDT 1998