SRAM FPGAs
Xilinx X4000 Family, New Virtex Family
- Virtex Family has up to 27,648 CLBs (1 M gates)
- Has both distributed SRAM memory in LUTs and blocks of RAM (4K blocks configurable to different data widths)
- Four onboard DLL (Delay Locked Loop) clocks, with clock doublers
- http://www.xilinx.com/prs_rls/vtxbackg.htm