Implicit 1-bit Prediction via caches

• Branch Target Access Cache

  • Cache accessed by address of branch instruction, contains Branch Target Address for that branch

• Branch Target Instruction Cache (BTIC)

  • Cache accessed by address of branch instruction, contains instruction located at Branch Target Address

• Either approach can be used, a HIT means that this branch was taken last time

  • No cache entries maintained for non-Taken branches

• Can be combined with 2 or 3 bit predictors

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