Effect of Branch on Pipelining
Assume a four-stage pipelined CPU
- Fetch, Decode, Execute, WriteBack
- Assume Execute stage used for zero test of register add r1, r2, r3 WriteBack beq r1, someplace Execute instr A Decode instr B Fetch
- By the time branch is executed, have already fetched instructions A, B
- Flushing A,B from pipeline introduces two bubbles in pipeline