Condition Code Checking (cond)
Condition Code Register approach
- Causes implicit linkages between instructions (instruction affecting CCR and the branch instruction)
- SuperScalar implementation must be aware of this linkage!!!
- Some superscalar processors use multiple CC registers! (IBM PowerPC has 8 CC registers) add CC0, r1, r2, r3 beq CC0, someplace
- Superscalar implementation must track dependency between instructions using the same CC register just like other register dependencies.