VHDL Model of Abstract Machine
Has 8 Entities
- fetch
- instmem (instruction memory)
- regfile (register file)
- execute (execution unit)
- memstage (memory stage)
- write (write back stage)
- datamem (data memory)
- processor (structural model which ties entities together)
The ‘abmtypes’ package defines all the types used in the VHDL model.