Objective:                

Implement the matrix multiply defined in Lab #7 in 12 clock cycles.  This will illustrate the resource versus time tradeoff in digital system design.

This lab is worth 50% more than previous labs (150 points instead of 100).

To Do                                                     

Implement the matrix multiply defined in Lab #7 in 12 clock cycles (the number of clock cycles that the busy line remains high during the multiplication operation). There are no resource limitations, use as many multipliers, adders, registers, RAMs etc as you want.    

You may chain the multiplier output in to the adder input as done in Lab #7; however you cannot chain successive multiply-add blocks together without an intervening register.

Hints

1. There are 16 multiply-add operations.  You must have at least 2 multiply-add blocks in order to perform the multiply in 12 clock cycles or less.
2. The more resources you use, the less complex your finite state machine will be.
3. An alternate way to do the computation is in column order.  Once you have X, you can perform the X*T00, X*T04, X*T08, X*T11 calculations in parallel instead of waiting for Y, W, Z and doing the X*T00, Y*T01, etc. calculations.

Checkoff

You must demonstrate to the TA that your design meets the requirements.                                                   

Report                             

1. You must hand in plots of all schematics, and print outs of your VHDL code. 
2. You must have a neatly drawn ASM chart that illustrates your FSM operation.   
3. You must have neatly drawn datatpath diagram of your design.
4. Compare the number of Logic Cells required for Lab #8 with your design of Lab #7.   Multiply the clock cycles by the number of logic cells for Lab8, and do the same for Lab #7.  Compare these two numbers (this is the area*time product, and is often used as a metric).