library ieee;
use ieee.std_logic_1164.all;

entity dff9 is
  port (  din:  in std_logic_vector(8 downto 0);
	  clk:  in std_logic;
      dout: out std_logic_vector(8 downto 0)
       );
 end dff9;

 architecture a of dff9 is
 begin

	main:process(clk)
	begin
      if (clk'event and clk='1') then  
	  -- rising edge of clock
	  dout <= din;
          end if;
        end process main;
 end a;