Issues in FPGA Technologies (cont)

• Macro elements

  • Are there SRAM blocks? Is the SRAM dual ported?
  • Is there fast adder support (i.e. fast carry chains?)
  • Is there fast logic support (i.e. cascade chains)
  • What other types of macro blocks are available (fast decoders? register files? )

• Clock support

  • How many global clocks can I have?
  • Are there any on-chip Phase Logic Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication?

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