Objectives:

To familiarize the student the student to the MOSIS scalable CMOS design rules and the basic CMOS layout concepts.

Set Up

Make a directory for your work. Change to this directory and execute the command:

 ln -s /ecad/local/tech/rel/gdt/scn08hp.dir/Ledrc

Design Rule Exercise

Figure 1 is a sketch of a CMOS circuit. Assume the minimum dimensions from the MOSIS design rules -- unless otherwise noted below. Use W=12 lambda and L=2 lambda for all transistors. Use a metal width of 8 lambda for the power buses, Vdd and Gnd. Use a poly interconnect pitch of 8 lambda in the channel region. Define the reference point at the center of the left source contact of the PMOS transistor as shown. Problems 1-10: What are the co-ordinates of the points indicated relative to the reference points provided. The numbers refer to the center of the contacts of vias except for #7 and #8 which refer to the end of the poly lines.

Layout Exercise

For the CMOS circuit shown in Figure 1, create the same layout in LED. Your file name should be as follows: lab6_yourlogin.L For instance if your login is smith, lab6_smith.L would be the name of the file. When LED prompts you for the name, don't include the .L, LED will assign this for you. Be sure to include your name on your circuit. Use the coordinates/dimensions which you determined in the previous section. Use minimum dimensions every where unless specified otherwise. Your circuit MUST pass both the internal LED DRC and external maskcheck DRC.

D. Function

Extract the hspice file for this circuit using the 'mcGdtExt' progrram. What function does the layout above represent? Explain how you arrived at this conclusion (i.e., explain how the circuit works, what is each transistor doing during certain inputs and how does this effect the output).