Lab3: Static Load Inverters


Introduction

The purpose of this lab is familiarize the students with the characteristics of static load inverters. You are to use spice as a 'testbench' for measuring the characteristics of these inverters, and then explain in the question portion what causes these inverters to act in the way that they do.

Setup

Look at the directory '~reese/EE4253/lab3'. The file 'models.sp' contains the transistor models you are to use for this lab. The 'nmos', 'pmos' models are to be used for the enhancement mode nmos/pmos transistors respectively. The 'ndep' model defines a depletion mode NMOS transistor (one of the static inverters requires this type of transistor as a load). The file 'noise_margin.sp' contains an example on how to measure noise margin for an inverter; it includes the file 'cmos_inverter.sp'.

Static Load Inverters

For all of the following circuits, unless otherwise stated, the length of all MOS devices should be 1.2U. At NO point should device widths be less than 2.4U. Set Vdd = 5 volts. Modify the 'noise_margin.sp' file to also measure the following values:

  1. Switching point (your first lab had an example of this)
  2. Lowest output value when input = Vdd.
  3. Highest output value when input = 0 v.
  4. DC current when input = Vdd.
  5. DC current when input = 0 v.
  6. Resistance of the load element when input = Vdd (static load inverters ONLY)
For each inverter, you will need to produce a plot as described below.

CMOS Inverter

Verify that your modified spice file works for the 'cmos_inverter.sp' case. Verify that the DC measurements meet the constraints as shown below.

PMOS Static Load Inverter

Simulate a PMOS Static load inverter (Gate is tied to GND) with the same Widths for the transistors as used for the CMOS inverter. Note that these 'W' values make for a fairly lousy inverter.

NMOS Depletion Load Inverter

Simulate an NMOS depletion load inverter (load is depletion NMOS, Gate,Source tied to output) with the same Widths as you ENDED up with for the PMOS static load inverter. Note that these 'W' values make for a fairly lousy inverter.

NMOS Enhancement Load Inverter

Simulate an NMOS enhancement load inverter (load is enhancement NMOS; Gate,Drain tied to Vdd) with the same Widths as you ENDED up with for the NMOS depletion load inverter. Note that these 'W' values make for a fairly lousy inverter.

Resistive Load Inverter

Create a resistive load inverter (the load element is a resistor). To choose a value for the resistor, look at the 'load resistance' plot that you produced for the static load PMOS inverter. Use the resistance value for Vin= Vdd as the load resistor value (if the PMOS effective resistance produced a good static PMOS inverter, then it should also be a good load value for this resistive load). The starting 'W' value for the NMOS pulldown should be the value you ended up with for the PMOS static load inverter.

Constraints

These are the constraints to be met when adjusting W values:
  1. Absolute value of both Noise margins > 0.5v (10% of Vdd)
  2. Absolute value of gain > 10
  3. Switching point between 1.5 v and 3.0v
If you can't meet all of the constraints, then sacrifice the constraints in the following order:
  1. One of the Noise margins can be reduced to > 0.25v (5% of Vdd)
  2. The switching point can be widened to 1.0v to 3.5v
Some of the inverters will be able to meet all of the constraints, others will not. Do your best.

Output Plot

For each inverter, when you arrive at the final W values, create a plot that has three panels. The three panels should plot Vin versus Vout, Load resistance versus Vin, inverter (drain) current versus Vin. For the normal CMOS inverter, do NOT plot load resistance versus Vin (the drain current will be near zero for certain ranges which will cause DC convergence problems if you try to calculate a resistance value). You will need to use the "Set Zoom" command in the 'Load resistance' panel to set the Y axis range to a reasonable range (select the panel, then click right and hold to get the local menu). The load resistance may vary WIDELY; you should set your Y-axis value so that the maximum Y axis value is 100K.

Answer the following questions.

Important! Most of your grade will depend on how you answer these questions,

  1. Rank the inverters by how well they satisfied the constraints.
  2. If an inverter was unable to satisfy all constraints, discuss why.
  3. In general for the static inverters, if the effective resistance of the load is held constant (the W is held constant), and the width of the NMOS pulldown is INCREASED, what happens to the noise margins?
  4. You measured the effective load resistance of the load device for the static inverters. From your DC measurement information, COMPUTE the effective 'on' resistance of the NMOS pulldown device when Vin = Vdd for each static load inverter. Show your work.
  5. From the drain current plots, discuss which inverters consume DC power and explain what conditions are necessary for this to happen. Rank the inverters in terms of DC current consumed (less is better).
  6. Which inverters could NOT pull the output all the way up to VDD. Why not?
  7. Which inverters could NOT pull the output all the way down to 0 v. Why not? What could be adjusted in the circuit to make the output go closer to 0 V?

To Turn In

  1. Answers to the questions.
  2. A plot for each inverter as discussed above.
  3. Final W,L values for your inverters.
  4. Final measured DC values as discussed above.
  5. A listing of your spice file.