LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Author: B.Reese entity bjdpath is port ( -- inputs signal clk: in std_logic; signal reset_b: in std_logic; signal load: in std_logic; signal clear_b: in std_logic; signal sel: in std_logic_vector(1 downto 0); signal card: in std_logic_vector(3 downto 0); signal acecard: out std_logic; signal score16gt: out std_logic; signal score21gt: out std_logic; signal score: out std_logic_vector(4 downto 0) ); end bjdpath; --************************************************************************* -- Architecture body --************************************************************************* architecture behavior of bjdpath is signal score_in, mux_out, score_out : std_logic_vector(4 downto 0); signal adder_out: std_logic_vector(5 downto 0); signal c: std_logic_vector(5 downto 0); begin score_ff:process (clk,reset_b) begin if (reset_b = '0') then score_out <= "00000"; elsif (clk'event and clk = '0') then score_out <= score_in; end if; end process score_ff; score_in <= "00000" when (clear_b = '0') else adder_out(4 downto 0) when (load = '1') else score_out; -- adder_out <= score_out + mux_out ; -- explicit ripple carry adder: process (score_out,mux_out,c) begin c(0) <= '0'; for i in 0 to 4 loop adder_out(i) <= score_out(i) xor mux_out(i) xor c(i); c(i+1) <= (score_out(i) and mux_out(i)) or (c(i) and (score_out(i) or mux_out(i))); end loop; adder_out(5) <= c(5); end process adder; mux_out <= "01010" when (sel = "00") else "10110" when (sel = "10") else '0' & card; acecard <= '1' when (card = "0001") else '0'; score <= score_out; score16gt <= '1' when (score_out > "10000") else '0'; score21gt <= '1' when (score_out > "10101") else '0'; end behavior; -- vhdl model for the control LIBRARY ieee; USE ieee.std_logic_1164.ALL; --************************************************************************* -- IO Interface Declaration --************************************************************************* entity bjcontrol is port ( -- inputs signal clk: in std_logic; signal reset_b: in std_logic; signal card_rdy: in std_logic; signal acecard: in std_logic; signal score16gt: in std_logic; signal score21gt: in std_logic; -- outputs signal hit: out std_logic; signal broke: out std_logic; signal stand: out std_logic; signal sel: out std_logic_vector(1 downto 0); signal score_clear_b: out std_logic; signal score_load: out std_logic ); end bjcontrol; --************************************************************************* -- Architecture body --************************************************************************* architecture behavior of bjcontrol is -- declare internal signals here signal n_state : std_logic_vector(1 downto 0); signal p_state : std_logic_vector(1 downto 0); signal ace11flag_in: std_logic; signal broke_in: std_logic; signal stand_in: std_logic; signal ace11flag_out: std_logic; signal broke_out: std_logic; signal stand_out: std_logic; signal card_rdy_dly: std_logic; signal card_rdy_sync: std_logic; -- state assignments are as follows constant get_state: std_logic_vector(1 downto 0) := "00"; constant add_state: std_logic_vector(1 downto 0) := "01"; constant test_state: std_logic_vector(1 downto 0) := "10"; constant use_state: std_logic_vector(1 downto 0) := "11"; constant add_10_plus: std_logic_vector(1 downto 0) := "00"; constant add_card: std_logic_vector(1 downto 0) := "01"; constant add_10_minus: std_logic_vector(1 downto 0) := "10"; begin -- flip-flops for control ff:process (clk,reset_b) begin if (reset_b = '0') then p_state <= "00"; ace11flag_in <= '0'; broke_in <= '0'; stand_in <= '0'; card_rdy_sync <= '0'; card_rdy_dly <= '0'; elsif (clk'event and clk = '0') then p_state <= n_state; ace11flag_in <= ace11flag_out; broke_in <= broke_out; stand_in <= broke_out; card_rdy_sync <= card_rdy; card_rdy_dly <= card_rdy_sync; end if; end process ff; broke <= broke_in; stand <= stand_in; state_machine: process (p_state, ace11flag_in, broke_in, stand_in, acecard, card_rdy_dly, card_rdy_sync, score16gt, score21gt) begin -- defaults here -- very important to put the defaults here if not then once set -- they remain set sel <= "00"; score_load <= '0'; score_clear_b <= '1'; hit <= '0'; n_state <= p_state; ace11flag_out <= ace11flag_in; stand_out <= stand_in; broke_out <= broke_in; case p_state is when get_state => if (card_rdy_sync = '0') then hit <= '1'; elsif (card_rdy_dly = '0') then stand_out <= '0'; broke_out <= '0'; if (stand_in = '1' or broke_in = '1') then score_clear_b <= '0'; ace11flag_out <= '0'; end if; n_state <= add_state; end if; when add_state => sel <= add_card; score_load <= '1'; if (acecard = '1' and ace11flag_in = '0') then n_state <= use_state; else n_state <= test_state; end if; when use_state => sel <= add_10_plus; score_load <= '1'; ace11flag_out <= '1'; n_state <= test_state; when test_state => if (score16gt = '0') then n_state <= get_state; elsif (score21gt = '0') then stand_out <= '1'; n_state <= get_state; elsif (ace11flag_in = '0') then broke_out <= '1'; n_state <= get_state; else sel <= add_10_minus; score_load <= '1'; ace11flag_out <= '0'; end if; when OTHERS => n_state <= p_state; end case; end process state_machine; end behavior; LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity bjack is port ( signal reset_b, clk, card_rdy : in std_logic; signal card: in std_logic_vector(3 downto 0); signal stand, broke,hit: out std_logic; signal score: out std_logic_vector(4 downto 0) ); end bjack; architecture struct of bjack is component bjcontrol port ( signal clk,reset_b, card_rdy, acecard: in std_logic; signal score16gt, score21gt: in std_logic; signal hit, broke,stand: out std_logic; signal sel: out std_logic_vector(1 downto 0); signal score_clear_b: out std_logic; signal score_load: out std_logic ); end component; component bjdpath port ( signal clk, reset_b, load, clear_b: in std_logic; signal sel: in std_logic_vector(1 downto 0); signal card: in std_logic_vector(3 downto 0); signal acecard, score16gt, score21gt: out std_logic; signal score: out std_logic_vector(4 downto 0) ); end component; signal load_net, clear_net : std_logic; signal sel_net : std_logic_vector (1 downto 0); signal s21gt_net, s16gt_net: std_logic; signal acecard_net: std_logic; begin c1: bjcontrol port map ( clk => clk, reset_b => reset_b, card_rdy => card_rdy, acecard => acecard_net, score16gt => s16gt_net, score21gt => s21gt_net, hit => hit, broke => broke, stand => stand, sel => sel_net, score_clear_b => clear_net, score_load => load_net); c2: bjdpath port map ( clk => clk, reset_b => reset_b, load => load_net, clear_b => clear_net, sel => sel_net, card => card, acecard => acecard_net, score16gt => s16gt_net, score21gt => s21gt_net, score => score ); end struct;