write_dlx.vhd

This is the VHDL code for the write stage of the DLX.
A Data Memory stall (wait) affects this stage differently because the wait is detected too late to prevent the writing to the registers
The wait is detected on the rising edge of the main clock; by this time, the write to the register file has already started. We have to let the current register file write take place
If the destination is the same as the 'A' side source then this will effect the zero flag value of the A side source
However, any logic looking at this zero flag value should be looking at the forwarded zero flag value. The register write will be repeated as long as mem wait is held
Other writes done is this stage are 'special' register writes, these are not protected by forwarding logic so we will have to inhibit these writes; inhibiting these writes will be done in at the register location, not from the load signal origination point