memoryD.vhd
This vhdl code is used for the synthesis of the data memory module
DMemOp
This indicates the operation type - byte, half word, word or
double word
DMemStart_L
This is an active low signal which is used for starting the
data memory access cycle
ByteSelect_L
It is a 4-bit signal which is used for selecting the
appropriate bytes of the data
MemWrite_L
It is an active low memory write signal
Databus
It is a bidirectional 32-bit bus that contains the data
Daddrbus
It is a 32-bit bus that contains the location of the data
DMemWait
It indicates whether the cycle is stalled