dlxregfile.vhd

This is the vhdl code for the synthesis of 32 X (32-bit) register file

It is a 32-bit load memory-data register bus which has the value to be loaded onto the register

Is a 32-bit data bus that contains the ALU output of the instruction which gets loaded onto the register in the WRITE stage.

Is a mux-select signal which chooses between LMDR and Destbus_b

5-bit address busses of the source registers of any ALU operation. These are actually sourced from the Instruction Register (IR)

5-bit address bus of the destination register

Load enable signal for the registers

Load enable signals for the two temporary registers, A and B respectively.

The output enable signals for the two temporary registers

The 32-bit data busses that has the tristated output of the temporary registers, A and B respectively.

The non-tristated outputs of temporary registers, A and B repectively

The zero-detect signal for the A-register