decode.vhd

This code is the control block for the decode stage of the DLX processor

Aload

Load enable signal of the A register in the decode stage

Bload

Load enable signal of the B register

PCmux

Select line of the PC multiplexer which selects between a 4-bit value,16 bit immediate and a 26-bit immediate.The output of the MUX is connected to the adder which adds this value to the PC value

Rsload

Load for the rs1, rs2 and the rsd registers

Rs_Select

Select signal for the multiplexer which selects the operation to be performed

RsdTypeSelect

MUX select signal which indicates whether the destnation value is an effective address or needs to be stored in the special register

NoExeFwd

Signal that inhibits forwarding logic for source values

BranchStall

Signal indicates a stall because load precedes a jump

sxt_imm

Signal to the dlxregs block indicates whether the immediate value needs to be sign extended

cp1oe

Signal that indicates a MOVS2I instruction