Microsystems Prototyping Laboratory

xorf201: 2 INPUT XOR

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------
A	B	O
-----------------
0	0	0
0	1	1
1	0	1
1	1	0
-----------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	12.5	30	89.2	41.7	26.1
B1	89.5	23	89.8	42.0	26.2
O	52	29.5	-	-	-
--------------------------------------------

• Delay Information