Microsystems Prototyping Laboratory

swcf120: T-GATE W / ACTIVE LOW ENABLE

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Hi-Z when CTL2 = 1

----------------------
CTL	DATA	O
----------------------
0	0	0
0	1	1
1	0	Z
1	1	Z
----------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CTL2	5	17	81.5	39.9	25.5
DATA1	25	40	120	94.1	77.0
O	33	19	-	-	-
--------------------------------------------

• Delay Information