Microsystems Prototyping Laboratory

swcf020: T-GATE W / ACTIVE HIGH ENABLE

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Hi-Z when CTL2 = 0

----------------------
CTL	DATA	O
----------------------
1	0	0
1	1	1
0	0	Z
0	1	Z
----------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CTL2	5	17	69.2	31.7	19.9
DATA1	25	40	128	101	83.1
O	33	19	-	-	-
--------------------------------------------

• Delay Information