Microsystems Prototyping Laboratory

oaif2201: 2 / 2 OR / NAND MUX

Gate Level Schematic of the standard cell "oaif2201".

Schematic of the standard cell "oaif2201" with device sizes in lambda.

Layout of the standard cell "oaif2201"

here.

Logic Equation: O = ((A1 + B1)) * (C2 + D2))'

Input(s): A1, B1, C2, D2

Output(s): O

Truth Table 

---------------------------------
A	B	C	D	O
---------------------------------
0	0	x	x	1
x	x	0	0	1
1	x	x	1	0
1	x	1	x	0
x	1	x	1	0
x	1	1	x	0
---------------------------------

Terminal Location and Capacitance Table 

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	52	25.5	71.6	35.4	29.9
B1	35	26	67.9	33.9	28.9
C2	25	32	56.4	28.1	25.7
D2	4	32	57.8	28.5	25.9
O	13	27	-	-	-
--------------------------------------------

Characterization Data