Microsystems Prototyping Laboratory

norf311: 3 INPUT OR / NOR

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------------------------
A	B	C	O1	O2
-----------------------------------
0	0	0	0	1
x	x	1	1	0
x	1	x	1	0
1	x	x	1	0
-----------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	5	24.5	68.0	34.7	29.3
B1	25	24	66.5	33.8	29.4
C1	39	25	70.6	35.6	30.2
O1	51.5	40	-	-	-
O2	13	24	-	-	-
--------------------------------------------

• Delay Information