Microsystems Prototyping Laboratory

lhsf311: D-LATCH W / SET & ACTIVE HIGH CLOCK

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Q-b = Qn'

------------------------------------------
CLK	DATA	SET	Q	Q_b
------------------------------------------
0	x	1	Qn-1	Q_bn-1
1	0	1	0	1
1	1	1	1	0
x	x	0	1	0
------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	20.5	28	75.2	55.9	35.3
DATA1	12	28	72.6	58.2	39.7
Q	123	28	-	-	-
Q_b	147	20	-	-	-
SET4	70.25	25	78.1	58.9	39.6
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information