Microsystems Prototyping Laboratory

lhbf311: D - LATCH W / SET, RST, & ACTIVE HIGH CLK

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

--------------------------------------------------------
CLK2	DATA1	RST3	SET4	Q	Q_b
--------------------------------------------------------
0	x	1	1	Qn-1	Q_bn-1
1	0	1	1	0	1
1	1	1	1	1	0
x	x	0	1	0	1
x	x	1	0	1	0
--------------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	40.5	20	72.3	55.9	45.1
DATA1	4.5	21	74.0	50.9	52.2
Q	167	26.5	-	-	-
Q_b	143	26	-	-	-
RST3	48.75	26	70.8	54.3	51.5
SET4	83	28.5	78.8	60.3	50.5
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information