Microsystems Prototyping Laboratory

lgrf311: D - LATCH W /RST & ACTIVE LOW CLK

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------------------------------------------
CLK2	DATA1	RST3	Q	Q_b
---------------------------------------------
1	x	1	Qn-1	Q_bn-1
0	0	1	0	1
0	1	1	1	0
x	x	0	0	1
---------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	40.5	24	77.4	52.9	49.2
DATA1	4.5	21	73.7	51.0	52.7
Q	144	26.5	-	-	-
Q_b	120	19	-	-	-
RST3	50	26	70.8	54.4	51.7
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information