Microsystems Prototyping Laboratory

lgnf311: D - LATCH W / ACTIVE LOW CLK

Gate Level Schematic of the standard cell "lgnf311".

Schematic of the standard cell "lgnf311" with device sizes in lambda.

Layout of the standard cell "lgnf311"

here.

Logic Equation: Q = (Qn-1 * CLK2) + (DATA1 * CLK2')

Input(s): CLK2, DATA1

Output(s): Q, Q_b

Truth Table 

----------------------------------
CLK2	DATA1	Q	Q_b
----------------------------------
1	x	Qn-1	Q_bn-1
0	0	0	1
0	1	1	0
----------------------------------

Terminal Location and Capacitance Table 

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	44	23	79.0	54.3	49.8
DATA1	4	19.65	70.5	57.2	48.8
Q	127	22.5	-	-	-
Q_b	103	26	-	-	-
--------------------------------------------

Characterization Data