Microsystems Prototyping Laboratory

labf211: NOR LATCH

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Q_b = (SET2' * RST1) + (Qn-1' * SET2' * RST1')

-------------------------------
SET	RST	Q	Q_b
-------------------------------
0	0	Qn-1	Qn-1'
0	1	0	1
1	0	1	0
1	1	0	0
-------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
Q	40	18	-	-	-
Q_b	16	18	-	-	-
RST1	49	20	72.2	35.9	23.3
SET2	7	20	72.2	35.9	23.3
--------------------------------------------

• Delay Information