Microsystems Prototyping Laboratory

labf111: NAND LATCH

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Q_b = (Qn-1 * SET2 * RST1) + RST1'

-------------------------------
SET	RST	Q	Q_b
-------------------------------
0	0	1	1
0	1	1	0
1	0	0	1
1	1	Qn-1	Qn-1'
-------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
Q	16	22	-	-	-
Q_b	40	22	-	-	-
RST1	48.5	38	61.8	29.7	19.3
SET2	7.5	38	61.8	29.7	19.3
--------------------------------------------

• Delay Information