Microsystems Prototyping Laboratory

invf171: ENABLED INVERTER W / RST

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

----------------------------------
EN2	DATA1	RST3	O
----------------------------------
x	x	1	0
0	x	0	z
1	x	0	DATA1'
----------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
DATA1	44	25	69.2	34.1	29.2
EN2	19	22	70.3	33.2	27.9
O	52	16	-	-	-
RST3	28	18	70.3	34.9	29.2
--------------------------------------------

• Delay Information