Microsystems Prototyping Laboratory

dfbf311: D-FF W / SET, RESET, Q & Q-b

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

Q-b = Qn' + RST3'

--------------------------------------------------------
CLK2	DATA1	RST3	SET4	Q	Q_b
--------------------------------------------------------
l2h	x	1	1	Qn-1	Qn-1'
h2l	x	1	1	DATAn-1	DATAn-1'
x	x	0	1	0	1
x	x	1	0	1	0
x	x	0	0	1	1
x	x	x	0	1	x
x	x	0	x	x	1
--------------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
CLK2	12.5	22	66.3	30.7	20.1
DATA1	41.5	45	46.0	21.4	12.9
Q	273	42	-	-	-
Q_b	252	34.5	-	-	-
RST3	113	18	80.0	34.4	20.7
SET4	81	24	87.0	40.1	23.8
--------------------------------------------

• Delay Information
• Hold Time Information
• Setup Time Information