Microsystems Prototyping Laboratory

delf011: DELAY CELL

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

---------
A	O
---------
0	0
1	1
---------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	13	43	51.7	24.1	15.3
O	142	36	-	-	-
--------------------------------------------

• Delay Information