Microsystems Prototyping Laboratory

buff121: TRI-STATE BUFFER

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-----------------------
EN2	DATA1	O
-----------------------
0	x	z
1	0	0
1	1	1
-----------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
DATA1	40.5	40	74.5	34.2	22.0
EN2	12.5	44	94.0	43.1	27.0
O	77	27	-	-	-
--------------------------------------------

• Delay Information