Microsystems Prototyping Laboratory

blf00101: 2 / 2 OR / NAND MUXLogic Cells

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-------------------------
A	B	C	O
-------------------------
0	x	x	1
x	0	0	1
1	1	x	0
1	x	1	0
-------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	31	20	62.6	30.0	21.3
B2	21	30	56.9	27.8	20.0
C2	4	30	58.0	27.9	20.5
O	13	31	-	-	-
--------------------------------------------

• Delay Information