Microsystems Prototyping Laboratory

blf00001: 2 / 2 AND NOR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

-------------------------
A	B	C	O
-------------------------
1	x	x	0
x	1	1	0
0	0	x	1
0	x	0	1
-------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	35	31	61.8	30.5	24.9
B2	21	29	57.2	28.1	23.6
C2	7	26	63.5	30.6	25.4
O	44	23	-	-	-
--------------------------------------------

• Delay Information