Microsystems Prototyping Laboratory

aof4201: 4 / 2 AND / OR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

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A	B	C	D	E	F	G	H	O
-----------------------------------------------------------------
1	1	x	x	x	x	x	x	1
x	x	1	1	x	x	x	x	1
x	x	x	x	1	1	x	x	1
x	x	x	x	x	x	1	1	1
0	x	0	x	0	x	0	x	0
0	x	0	x	0	x	x	0	0
0	x	0	x	x	0	0	x	0
0	x	0	x	x	0	x	0	0
0	x	x	0	0	x	0	x	0
0	x	x	0	0	x	x	0	0
0	x	x	0	x	0	0	x	0
0	x	x	0	x	0	x	0	0
x	0	0	x	0	x	0	x	0
x	0	0	x	0	x	x	0	0
x	0	0	x	x	0	0	x	0
x	0	0	x	x	0	x	0	0
x	0	x	0	0	x	0	x	0
x	0	x	0	0	x	x	0	0
x	0	x	0	x	0	0	x	0
x	0	x	0	x	0	x	0	0
-----------------------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	7	24	65.4	30.9	25.5
B1	17	26	56.4	27.2	23.1
C2	33	29	59.6	29.0	23.9
D2	54.25	31	48.5	23.0	21.0
E3	89	31	64.3	30.4	25.2
F3	104	26	58.1	28.0	23.5
G4	114	27	56.9	27.6	23.2
H4	132	25	62.0	29.5	24.6
O	73	19	-	-	-
--------------------------------------------

• Delay Information