Microsystems Prototyping Laboratory

aof2401: 2 / 4 AND / OR MUX

• Gate Level Schematic
• Transistor Level Schematic
• Layout
• Logic Equation
• Inputs
• Outputs
• Truth Table
• Terminal Location and Capacitance
• Characterization Data

here.

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A	B	C	D	E	F	G	H	O
-----------------------------------------------------------------
1	1	1	1	x	x	x	x	1
x	x	x	x	1	1	1	1	1
0	x	x	x	0	x	x	x	0
0	x	x	x	x	0	x	x	0
0	x	x	x	x	x	0	x	0
0	x	x	x	x	x	x	0	0
x	0	x	x	0	x	x	x	0
x	0	x	x	x	0	x	x	0
x	0	x	x	x	x	0	x	0
x	0	x	x	x	x	x	0	0
x	x	0	x	0	x	x	x	0
x	x	0	x	x	0	x	x	0
x	x	0	x	x	x	0	x	0
x	x	0	x	x	x	x	0	0
x	x	x	0	0	x	x	x	0
x	x	x	0	x	0	x	x	0
x	x	x	0	x	x	0	x	0
x	x	x	0	x	x	x	0	0
-----------------------------------------------------------------

--------------------------------------------
Name	X_loc	Y_loc	   Capacitance (fF)
	lambda  lambda   2U	1.2U	0.8U
--------------------------------------------
A1	49.15	23	63.8	31.2	22.1
B1	30.95	28	63.1	30.5	22.6
C1	16	23	62.0	29.8	22.7
D1	5.8	21.5	69.4	33.1	23.3
E2	137.15	27	63.8	31.2	22.1
F2	118.9	28	63.1	30.5	22.6
G2	104	23	62.0	29.8	22.7
H2	94.5	22.5	69.2	33.0	23.3
O	72	29	-	-	-
--------------------------------------------

• Delay Information