MSU SCMOS/GCMOS Release Overview (April 1997)

This distribution site contains cell libraries built around the Mentor GDT tools and compatible with the MOSIS processes. What follows is a brief description of the files available on this distribution site.

Mentor GDT Tech Files

This tar file contains the tech files for the Mentor GDT tools for all of the MOSIS processes (0.5u to 2.0u). The tar file also contains some scripts for performing mask-level DRC, mask-level LSIM transitor netlist extraction, mask-level HSPICE transistor netlist extraction, and layout versus schematic checking. These scripts provide easy interfaces to the GDT tools that peform these various tasks. The scripts can be found in the 

  tech/rel/ckmt/bin
directory once the tar file is unpacked.

SCMOS Library

The SCMOS library is an older cell library that is upward compatible with the ITD/AuE cell library that has been distributed with the Lager toolset. It provides the standard combinational gates along with several complex boolean functions such as and-or-invert, or-and-invert, 2to1 mux, etc. It also has a good set of storage elements. Only the inverter and buffer cells are available in multiple drive strengths. The distribution is broken into 4 sections:
  1. Documentation
  2. VHDL Models - uses 'std_logic' type, tested within the Mentor QHDL (Model Tech) VHDL environment
  3. Mentor GDT layouts and schematics; also contains the cells in GDSII format.
  4. Synopsys synthesis files - contains synthesis files that has timing information based on the Orbit 1.2 Nwell process, and HP 0.8 process, both available via MOSIS.
The SCMOS cells violate the minimum spacing between MPOLY (Met1-Poly) contacts and M1M2 Vias (MOSIS Rule 8.5b) but this has not proven to be a problem in any of the designs we have fabricated.

GCMOS Library (distribution will be ready in June 1997)

The GCMOS library is a new library that has been created using the Mentor ICGEN Cell generation system. This library only has a minimum set of cells (inverter,buffer, 2/3/4 input Nand, tri-state buf, DFF, xor2, and2, or2) but each member is available in 9 drive strengths. Some of the cells are available in two different architectures giving a choice of 18 different drive strengths. Large, Synopsys-synthesized blocks have significantly higher performance when implmented in the GCMOS library rather than the SCMOS library. The area performance is about the same for large designs (>2000 cells); for small designs the SCMOS designs requires less area than the GCMOS designs.

We are in the final verification stages for this library; our plans are to release it in June.

Mentor GDT Memory Builder Blocks

These are miscellaneous parameterized blocks that have been created using the Mentor GDT Memory Builder tool. Memory Builder is a cell tiling tool for creating parameterized tiled layouts.

Questions about the Release

The MSU SCMOS/GCMOS FAQ is a good source of information; we use this FAQ for our VLSI classes so some of the pathnames mentioned in the FAQ are MSU specific but translation to your local pathnames should not be too hard. Email can also be sent to reese@erc.msstate.edu.