PadFrame Generator Tutorial


The procedure for running the padframe generator:

PadFrame Environment Setup

   setenv PadFrameGen /projects/mpl/cddd/tools/src/padframe_gen/src
   set path = ($path /projects/mpl/cddd/tools/src/padframe_gen/src)
(if you are using the ERC admin 'swsetup' tool, the path setting 
 above should be:
   set tpath = (/projects/mpl/cddd/tools/src/padframe_gen/src)
)

Hierarchic Schematic Creation

  1. Your top level schematic must have 8 padframe blocks surrounding the core:
     left block, top-left block, top block, top-right block,
     right block, bottom-right block, bottom block, and bottom-left block
     of which top-left, top-right, bottom-left, and bottom-right blocks are corner blocks.
     -- Each of the side blocks are made up of Pad/Buffer instances (icons of the schematic)
     -- INOUT terminals have to be placed on the sides of each side block for routes
        that run around the corners of the chip (i.e. ngnd).
  2. The cell name of a schematic must be the same as its corresponding layout.
     -- It is case sensitive.
  3. Terminal names in a schematic cell must be same as those in a layout cell.
     -- It is case sensitive.
     -- It is not necessary to create the layouts for the side blocks (i.e. left,right,etc.)
        the generator will create these for you.
  4. The orientation of an instance in the schematic cell of a pad must be the
     same as in its corresponding layout cell.

NOTE: #2,#3, and #4 are the cause for most of the problems encountered in PadFrameGen. Be sure to pay close attention to these.

Core Layout

The core layout should be created and saved as cells and leaves. (see the AutoCells tutorial)

Preparing to Run PadFrameGen

In your working directory, You should have the following five files before running padframe generator. One of these files is technology dependent. Make sure you get MicroRoute.par for the appropriate technology. 
 
 MicroRoute.par -- contains information about the technology for MicroRoute.
	           it can be obtained from :  

                   /projects/mpl/cddd/cell_libs/scmos/mentor/MicroRoute
 
 NOTE: This same file can be used for scmos and gcmos cell libraries.

 assemble_chip.m -- copy it from the tutor directory:

                  /projects/mpl/cddd/tools/src/padframe_gen/tutor/scn12hp
 
 layout_inc -- a user created file that batch loads all the layout cells for a design
               an example is included in the tutor directory

 schematic_inc -- batch loads schematic cells for a design
                  an example is included in the tutor directory
                  
 pad_location.par -- pad location and power parameter file  created by user.
	             an example is included in the tutor directory
 
                     For a minimum size padframe, the flag in the file is set to 0.
		     For a core limited design, you have to set the flag to 1.
NOTE: Padframe Generator only recognizes the pad_location.par file (filename and format is important in this file).

Starting PadFrame Generator

Enter the following command on the command line 
    run_padframe technology design_name
    i.e.
		 run_padframe scn12hp chip

Debugging

After running Padframe generator, Led creates a bunch of information under the Debug subdirectory. It may be helpful for debuging your design.

Did you test your layout_inc and schematic_inc files to make sure all cells are getting loaded?

Did you pay any attention to #2, #3, and #4 above?
Check to make sure everything corresponds.

Some Notes on designing a Pad Library for use with PadFrame Generator

  • Layers can't extend past the terminals on the edge of the Pad cells.
  • Make sure that after a pad instance and a buffer instance are tiled together they are still on grid. This is a very easy mistake to make. This also goes for tiling side-by-side.
  • Make sure the corner layout is large enough to keep the top/bottom and left/right sides from overlapping.

    good luck ;)

    Double PadFrame Generator

    Double PadFrame Environment Setup

       setenv PadFrameGen /projects/mpl/cddd/tools/src/padframe_gen/doublepad/src
   set tpath = (/projects/mpl/cddd/tools/src/padframe_gen/doublepad/src)
    You'll be using a different set of pad schematics and layouts. All of the necessary files can be found in: 
    	/projects/mpl/cddd/tools/src/padframe_gen/doublepad/tutor

    Starting Double PadFrame Generator

    Enter the following command on the command line 
        run_double_padframe technology design_name
    i.e.
		 run_double_padframe scn06hp chip

    Differences in PadFrame_Gen and Double PadFrame_Gen

    As far as functionality goes everything stays the same except for an added feature. This feature can be noted in the pad_location.par file. The double padframe generator can support multiple vdd/gnd/ngnd pads. I strongly urge the user of the double padframe generator to be very familiar with the way padframe generator works before attempting to use the double padframe generator.