The ARPA and NSF research communities have traditionally used libraries of cells with fixed geometries and fixed, but scalable, design rules for their designs. These library cells of fixed geometry facilitate expedient implementation with CAD tools, e.g., Wolfe and Lager, etc., for general logic but suffer the following deficiencies:
Fundamentally, the research community needs as part of its infrastructure a general approach to constraint driven digital design which provides
Layout generators, which support both parameterizable design rules and device sizing, provide the means to quickly adapt to the changing requirements of the constraint driven designs. However, utilities to optimize the device sizes for performance or power and to quickly characterize in support of accurate system timing simulations are also required.
Clearly, the use of parameterized generators to generate the optimum" instantiation of a circuit brings more challenges to the designers. A CAD utility to determine these device sizes, given the design constraints, is required. This issue must be researched and resolved, possibly in phases, and represents the development of a suitable design methodology to utilize this extra design flexibility.
In addition, the instantiations of the leaf cells must be compatible with assembly from multiple CAD tools with good results for a variety of applications.
It should be understood at the outset that the dlm3.0 version of the ITD (Institute for Technology Development) library supports two layer metal in the scalable rules down to the 0.8 micron technology. This library has been well characterized with accurate timing and VHDL models by Mississippi State University and is being made available to the ARPA/FBI/NSF communities at the present time under contractual rights defined in the last subcontract to ITD from MSU.
There are both short and long term objectives in this research. The short term objective is to provide vendor independent CMOS and BiCMOS libraries which are accurately characterized and modeled for VHDL simulations for below the 0.8 micron technology with three layers of metal. The selection of cells and the technology will be made with MOSIS. An entry level set of BiCMOS cells are anticipated to be defined from commercial designs.
The long term objective is to provide, as outlined above, a general approach to constraint driven digital design which provides compatibility with CAD tools from multiple sources, efficiency in design time and costs for prototyping, dense layouts for cost effective fabrication, and flexibility to configure to the specific requirements. Essential ingredients in meeting this objective are
Technology evolution and the extreme requirements in application results place considerable burden on our design methodologies. Developing application specific libraries with application specific CAD tools is not only costly but also time consuming. Yet, the ability to capture the benefits from the manufacturing successes in the commercial industry is quite important. Flexibility in moving across foundries and across technology is vital. This research strikes at the heart of automating" physical design to optimally" satisfy the different application needs across the various fabrication technologies and vendors in a generic manner. This will become even more vital to embedded microsystems in the future as technologies evolve.
There are several keys to the puzzle. One is the effective use of third metal interconnect to improve layout density; it is also vital that this third metal interconnect be used in a generic manner which proves adaptable to CAD tools from multiple vendors.
The second is the ability to capture in a relatively straight-forward manner algorithms for the automatic and parameterizable generation of leaf cells from a netlist or equivalent. The key to good layout is the planning. After extensive experience in layout (over 30 years), the PI has developed an understanding of the relevant issues and means to achieve the design goals efficiently and effectively. A VLSI Design class paper is attached to provide insight into these principles for the students. The PI has laid out in symbolic form selected logic functions defined in the ITD/MSU library. Those selected were chosen based on being representative of all of the cells. A cell takes perhaps two minutes to two hours, with the average taking perhaps 30 to 45 minutes to lay out in a symbolic form. Students are using these to implement a new library. In addition, the students are using the design guideline as an algorithm reference for other cells to look for shortcomings. From these exercises the PI is convinced that a general purpose algorithm can be developed that is compatible with the third level metal utilization and supports parameterizable leaf cell generation. In addition, the placement algorithm is not limited to traditional CMOS with traditional Phillips style of layout. The algorithm has also demonstrated remarkably good results with circuitry of the mostly NMOS type, e.g., Complimentary Passgate Logic CPL. These circuit and layout technologies are important and most evolve with time.
The third key relates to a straightforward manner to arrive at device sizing given the constraints of the design. First, there are known empirical methods that many people use, e.g., Cypress Semiconductor designers use such methods in implementing their high performance circuits, most of which are hand crafted for speed. Second, analytical approaches to this optimization problem are in the literature with various solutions used in the industry; however, most are based on approximations which lead to imperfect results, although reasonable for various situations. The optimum results for high performance along the critical path corresponds to a minimum delay in design space for which a small change on any one size makes little difference in the overall results; consequently, even compromised or empirically driven results may well be close to the optimum. On the other hand, for low power applications the size constraints on the non-critical signal paths may well be the minimum size defined by the physical design rules. The real question is not whether or not good algorithms can be created for sizing, but rather, how close to optimum can the results be?
The fourth key relates to the efficient integration of the above technologies into the top down design process, particularly using synthesis. We do not know the best way to deal with the extra flexibility at this point. Perhaps creating a generic timing model is best. If so, then the macromodeling research effort must include the variables to define the circuit and sizing issues and perhaps extend to cover the operating conditions, e.g., power supply, temperature, and process models. On the other hand, the straight forward approach is to create discrete instances of the library functions, characterize, and use in a more, or less, conventional manner at the synthesis level. At the physical level one then creates the desired instance. Perhaps, at this latter stage a final device sizing algorithm should be run for optimization. Again, the question is not so much: can a design methodology with CAD utilities be developed? But rather: what are the costs, and how close to optimum can the final results be, given the design constraints?
The project objectives can be achieved. The real questions relate to how close to the ideal will the results be?