G. Statement of Work

By October of 1994, the first prototype version of the layout generator will have been developed, utilizing the dissertation efforts of Sanjay Rekhi and master level projects of three other students. This version provides good placement now, but is being constantly compared with the PI's handcrafted symbolic designs of representative cells from the existing ITD library. As we face new circuit circumstances, we modify the algorithm to provide the same results as in the handcrafted design. Other students are completing the fixed designs. The routing algorithm is being studied by another student with consideration for adapting an existing tool such as YACR with a prototype functioning presently. We will also be investigating the direct creation of a routing utility based on the handcrafted experiences. We are using a modular approach to the generator construction with either a schematic input or a symbolic description of the cell. The place and route algorithms create a symbolic description of the cell. A general layout utility is used to create the final cell layout based on the symbolic description and the design rules. In this manner, we can take a library of symbolic descriptions and updated design rules (perhaps with minor updates to the method) and create a new library customized and transparent to the differences in the design rules. The goal is to not sacrifice any area or performance over the handcrafted design methods.

G.1 Layout Generator for Leafcell Layout with Compatibility to Third Layer Metal

At the start of the contract, additional cells associated with the libraries identified with this research will be designed using both the methods identified above: one handcrafted from the PI's symbolic design and another using the initial version of the the place and route algorithms from above. The comparative results will drive the layout generator development. Experience with handling the variable design rules and the parameterized device sizes will be also be incorporated. As the libraries evolve, the capability of the layout generator will incorporate new features and will yield improved results comparable to handcrafted.

  1. The prototype of an automatic design rule independent layout generator for standard cells will be developed using GENIE (Mentor Graphics) suitable for two or three layers of metal. The layout generator will synthesize layouts from a structural representation of the cell. [YEAR 1]
  2. The modular development of the program, as shown in NO TAG, will allow the capture of user defined transistor placement and routing, in addition to the automatic placement and the routing. The functionality required to support both the methods for layout generation with referenced set of design rules will be added. [YEAR 1]
  3. The creation of the fixed libraries below will lead to refining the algorithms, methods, and improved user control. [YEAR 2]
  4. A portable tool to support the non-GDT users which incorporates the place and route algorithms developed above will be developed. [YEAR 3]

G.2 CMOS Standard Cell Library

After reviewing the new design rules with MOSIS for a selected technology, the MPL will create a conventional fixed transistor implementation for each library cell. These cells will be characterized and macromodeled accurately for inclusion into the event driven simulation models, e.g., VHDL. On a near term basis, the fixed versions of the libraries will be designed to the newly revised MOSIS design rules in support of the next HP and IBM technology level with support of three layer metal. The effort has two benefits: it provides the advanced libraries for conventional use and provides the means to drive the final version of the layout generator.

G.2.1 HP Standard Cell Library

The functional definitions in the HP library, with perhaps two to three times the number of cells as in the ITD library, facilitates enlargement of the present library. Re-layout of the HP library, starting with the functional or circuit specification, can provide a vendor independent enhancement. There clearly is an overlap of equivalent cells in the two libraries. The decision to duplicate actual cells of equivalent function, duplicate simply the terminal labeling, or simply not duplicate at all will be made in conjunction with MOSIS. Users utilizing existing libraries will not welcome having to rework the CAD tool support utilities and their existing designs simply because of labeling. Dual labeling may be sufficient. These selected cells from the HP library are to be redesigned, characterized, and included in a new three layer metal compatible library.

  1. The additions from the HP library will be redesigned in a conventional fixed transistor implementation form (three layer metal), but supportive of design rule independence. [YEAR 1]
  2. This expanded library will be characterized with timing models developed for the conventional fixed implementation. [mid YEAR 2]
  3. In support of generic macromodeling of the timing for parameterized generator cells (over a reasonable range) required in synthesis, research will focus on how to include the additional variables of stage sizing, fan-in, etc. Characterization methods, models, and data will be developed. [YEAR 2 & 3]

G.2.2 MSU Standard Cell Library

The historical usage of the ITD library, based originally on NSA's library, encourages the migration of the library to the submicron three layer metal technologies. Historically, a major cost factor has been accurate characterization for timing in support of varying input transition times; this task has now been reasonably well automated, but still consumes considerable computer time.

MSU enlarged the ITD library for internal use in order to support asynchronous and miscellaneous other designs. These extra MSU cells are to be redesigned, characterized, and included in the new library.

  1. The MSU expanded library, which includes the ITD cell library as a subset, will be redesigned with design rule independence and parameterized device sizing compatible with the three layer metal policy. [YEAR 2]
  2. This expanded library will be characterized with timing models developed for the conventional fixed implementation. [YEAR 2]
  3. In support of generic macromodeling of the timing for parameterized generator cells (over a reasonable range) required in synthesis, research will focus on how to include the additional variables of stage sizing, fan-in, etc. Characterization methods, models, and data will be developed. [YEAR 2 & 3]

G.2.3 Data Path Cell Library

Additional cells will be added to the library which correspond to the Hyper/Lager data path cells in function. These cells facilitate using the three layer metal standard cell" conventional place and route tools to create data paths. With the addition of parameterizable transistor sizing, datapaths will be easily customized to the particular constraint driven requirements in a generic manner. These datapath cells from the Hyper/Lager library are to be redesigned, characterized, and included in a compatible library.

  1. MSU will design the approximate 20 functions defined in the Hyper/Lager datapath library with design rule independence and parameterized device sizing compatible with the three layer metal policy. [YEAR 2]
  2. This expanded library will be characterized with timing models developed for the conventional fixed implementation. [YEAR 2]
  3. In support of generic macromodeling of timing for parameterized generator cells (over a reasonable range) required in synthesis, research will focus on how to include the additional variables of device sizing, etc. Characterization methods, models, and data will be developed. [YEAR 2 & 3]

G.2.4 BiCMOS Standard Cell Library

As MOSIS makes the BiCMOS technology available for experimental use, MSU will be engaged in experimenting with the technology. MSU has the Cypress Semiconductor 0.8 micron BiCMOS technology files already created in the GDT and Checkmate tools. They must be modified for MOSIS compatibility.

  1. The necessary technology related files associated with the MOSIS/IBM BiCMOS technology, required for schematic and layout capture, simulation, design rule and electrical rule verification in support of GDT and Checkmate, will be created and demonstrated with example designs through MOSIS. [YEAR 1]
  2. A set of base-line BiCMOS cells (commonly used by Cypress Semiconductor) and designed compatible with the MOSIS/IBM technology will be provided. [YEAR 2]
  3. High performance BiPolar I/O compatible cells will be designed. The BiCMOS library of cells will be characterization and with timing modeled. [YEAR 3]

G.3 CAD Tool Interfaces

The issue of library compatibility across the multiple vendors must be established. The Lager tools with TimberWolfe/YACR, Mentor's GDT, and Cadence are all important tool suites used in the community. The activities below are aimed at establishing this compatibility. Cascade can be supported separately through a willing user in the community.

  1. MSU will install and modify as necessary in the TimberWolfe/YACR tools the new three layer metal library. [YEAR 1]
  2. MSU will install and modify as necessary in the Mentor tools the new three layer metal library . [YEAR 1]
  3. MSU will investigate and design demonstration datapaths using the standard cell generator for low power and high performance applications, using the functions defined in the Hyper/Lager IV DPP library and using the Hyper synthesis interface. [YEAR 2]
  4. MSU will install and modify as necessary in the Cadence tools the new three layer metal library. [YEAR 2]
  5. MSU will create demonstration datapath designs in the two commercial CAD tools using the standard cell generator for low power and high performance applications and using the Hyper synthesis interface. [YEAR 3]
  6. MSU will modify and update as necessary the interfaces into the three CAD tool suites identified in support of the parameterizable cell library. [YEAR 3]

G.4 Constraint Driven Design Methodology

A methodology for integrating transistor-parameterizable cells into a constraint driven design system is to be developed.

  1. Research and utilize the best currently available methods for optimizing device sizes along given signal paths and given particular CMOS circuitry to meet both delay and power constraints. [YEAR 1]
  2. Develop delay and power macromodels and characterization methods for parameterizable blocks containing variable transistor size components. [YEAR 1]
  3. Integrate the macromodels in a currently available synthesis system -- the current choice for the synthesis system is HYPER. [YEAR 1]
  4. Investigate algorithms to determine for optimization purposes the critical and near-critical paths (and their interactions) that do not meet the timing criterion, e.g., an asymptotically optimal near-critical path algorithm. [YEAR 2]
  5. Develop a post-route layout tool for fine-tuning transistor sizes to optimize speed and power characteristics without perturbing routing to a significant degree [YEAR 2].
  6. Demonstrate the methodology for several significant datapath intensive designs using the HYPER synthesis system [YEARS 2-3].