There are both short and long term results in this research which correspond to the objectives. The short term objective is to provide vendor independent CMOS and BiCMOS libraries which are accurately characterized and modeled for VHDL simulations for below the 0.8 micron technology with three layers of metal. These three layer metal CMOS and BiCMOS libraries will be available for use by the ARPA and NSF communities using a conventional standard cell design methodology, which is important in the short term if not for the long term. The selection of cells and the technology will be made with MOSIS. Transforming the current Hewlett Packard library to a vendor independent version and characterizing to the appropriate vendor technology is a serious consideration as the CMOS solution". The timing models developed from the characterization would also be available for Verilog modeling. An entry level set of BiCMOS cells is anticipated to be defined from commercial designs, e.g., Cypress Semiconductor. The community would have a BiCMOS library to begin using as the BiCMOS technology is made available by MOSIS.
The ARPA/NSF research community will have available to use, based on the long term objectives, a general approach to constraint driven digital design which provides
The community will have available for its use in various applications, which require an extensive range of power and performance, the following CAD tools, utilities, and data with a demonstrated design methodology:
Layout generators, which support both parameterizable design rules and device sizing, provide the means to quickly adapt to the changing requirements of the constraint driven designs. However, utilities to optimize the device sizes for performance or power and to quickly characterize in support of accurate system timing simulations are also required. Both constraint driven designs and flexibility to quickly adapt to changes in the technology will become possible.
In addition, the instantiations of the leaf cells must be compatible with assembly from multiple CAD tools with good results for a variety of applications. With control of relative cell placement and with utilization of the third level of metal, place and route of rows of cells provides a general approach to fairly dense logic and is supported by multiple CAD vendors. Particularly for prototyping, even datapath logic can be efficiently and flexibly implemented, given the appropriate logic leaf cells, e.g., the Lager definitions. Historically, standards cells utilized in this manner have been fixed cells for general purpose usage, resulting in inefficient, suboptimal designs. The use of metal 3, which can result in the channel routing on top of the active circuitry in the leaf cells, and the use of parameterizable cells change this result significantly. The community will have more flexibility in adapting to new vendor CAD tools with satisfactory prototyping results across a greater variety of applications.
Clearly, the use of parameterized generators to generate the optimum" instantiation of a circuit brings more challenges to the designers. A CAD utility to determine these device sizes, given the design constraints, is required. However, the use of this utility presumes a logic and circuit definition. How does one synthesize the logic, given the overall logic constraints? The synthesis tools presently select from a selection of cells. Does one model the general timing of the leaf cell generators (or generator), possibly creating a distribution of conceivable instantiations from which the synthesis tool makes its selection? Can one actually create a general purpose macromodel with which the synthesis tool operates? These are issues that must be researched and resolved, possibly in phases, and represent the development of a suitable design methodology to utilize this extra design flexibility. The base level tools are more straightforward to develop at this time than the all encompassing design methodology which is best for all situations for all applications. At the very least, these base level tools provide the foundation for the community to evolve the design methodologies in search of optimized constraint driven designs. In addition, we are confident that a good demonstration design methodology will be made available to the community.
In summary, three layer metal CMOS and BiCMOS libraries will be available in order to take advantage of these new technologies. Quality digital system designs can be efficiently achieved, satisfying a variety of constraint requirements, particularly for prototyping, if not volume production. It will not be necessary to develop separate application specific libraries. It will not require such extensive efforts and time to adapt to the new technologies and application requirements as presently.