Industrial firms employ some of the methods in this proposal. For example, Cypress Semiconductor utilizes manually driven empirical methods to size their transistors in the performance sensitive signal paths. We propose to automate the design decisions and link into the appropriate CAD tools. Ross Technology utilizes GDT generators for their standard cell logic for their SPARCt processor chips to handle the changes in design rules as they migrate to new technologies. Ross creates specific instances of logic cells to provide stage sizing for optimum drive for different loads. These instances are well characterized for timing and used for accurate system simulations. Synopsis supports such granularity in logic cells as a means to optimize, or at least improve the logic synthesis. Other industrial firms, such as AT&T, have reported internal use of layout generators which support device sizing. However, the ARPA research community only uses fixed design libraries with scalable design rules. The use of these extensions in design concepts by the ARPA community is at best isolated and essentially limited to handcrafted designs. The distinguishing factor of our proposed work is that we would like to take these concepts and integrate them into a complete system - from library development to methodology of use within a state of the art, high level synthesis toolkit. We will draw heavily on the work of others in the areas of automatic layout generation, optimal transistor sizing, and module characterization.
At least two commercial versions of CMOS layout generators have been introduced to the market place: Caeco (acquired by Silicon Design Lab, then Silicon Compiler Systems, and then Mentor Graphics) introduced their product about four years ago, but were limited to traditional CMOS with a Phillips style of layout. This tool used only straight poly crossing a single row of NMOS and a single row of PMOS transistors. The product was not intended for standard cells design, but supported the designer in assembling structure into handcrafted designs. Support for the product was discontinued with the product pulled from the market.
Cadence has recently introduced an automatic layout generator which gives reasonable results for traditional CMOS circuits. Non-traditional CMOS layouts do not fare as well with the tool. As an example, an evaluation at MSU compared a handcrafted design by an expert layout engineer employed by Cypress to the automatically generated layout produced by the Cadence tool. The design contained transmission gates which do not lend themselves to traditional layout styles. The comparison showed the handcrafted design to be 50% smaller than the generated layout. We postulate that other non-traditional layout styles such as Complementary Passgate Logic CPL or other NMOS mostly styles of circuitry will further highlight shortcomings. We believe that there is still work to be done in the area of cell-based layout generation, especially in the areas of non-traditional CMOS design styles.
MOSIS is also evaluating the Cadence tool for use in redesigning the HP library to be vendor independent. The JK flip/flop used in the attached student tutorial came from MOSIS as part of this evaluation. If the determination is that the Cadence tool does provide good results for the three layer metal philosophy, then it becomes an alternative to our proposed layout generation tool -- at least for creating a new library. Discussions will continue with MOSIS with the possibility that MOSIS will want to undertake the redesign of the HP library. If that is the case, there should be standards established to ensure the compatibility across other libraries, in terms of physical dimensions and documentation for the user. By MSU continuing with the characterization and the integration into the CAD tools, this could be handled. In any case, MOSIS is expected to be involved in the activities -- much the way MSU has worked with UCBerkeley in the past on the FBI project.
The method of generating one dimensional functional cell was first proposed by Uehara and vanCleemput [3], who developed a heuristic for solving the minimum width problem with circuit reordering. The graph models consists of two series-parallel multigraphs, one for the NMOS pulldown and the other for PMOS pullup. The process of finding the minimum width layout is to add pseudo-edges" to the graph model G to ensure that the new graph GE possesses a dual Euler trail. The algorithm then finds the dual Euler trail in the pullup and pulldown multigraphs, where original edges of G correspond to transistors and the pseudo-edges correspond to diffusion gaps. This heuristic does not find the minimum width under all circumstances. This algorithm has been extended by Nair et al.[4], who breaks the graph into smaller subgraphs, where the order of the subgraph is fixed, and finds the dual trails in the subgraphs. The subgraphs are then combined together to merge as many subgraphs as possible. The second algorithm developed by Nair et al.[4] is similar to the one developed by Madsen[5], and produces an optimal layout under some special cases. Other algorithms developed by Ong et al.[6] and Hayes and Maziasz[7] first pair the PMOS and NMOS transistor and then merge the transistors pairs to produce an optimal solution.
To ensure an optimal layout for different cell implementations, we use fundamental graph theoretic concepts to find the dual or single chains of transistors from the schematic. Special consideration is given to pass gates and similar gates, where the PMOS and NMOS transistors do not share the poly, i.e., the PMOS and the NMOS are not paired. The graph is treated as a collection of various components, with each component connected at Vdd and GND. An optimal transistor chain is found for each component. The various chain(s) are then merged to minimize routing and maximize diffusion sharing. This approach is considerably different from others and allows single or dual transistors trails to be found for a circuit consisting of dual/non-dual NMOS and PMOS transistors and circuits consisting of disconnected PMOS and NMOS components, e.g., CPL, etc.
In terms of the overall design methodology for utilizing cells with variable transistor sizing, MSU is not aware of any similar work within the ARPA/NSF community which provides the same system approach proposed here. The proposed integration of the methodology into the Hyper system provides an interesting vehicle for proof of concept. The extra degrees of freedom provided by the methodology should provide HYPER with an improved capability to perform constraint driven design. The proposed work also supports the continuation of designs based on the NSA/ITD library heritage with the prescribed extra flexibility.
The proposed work also supports MOSIS bringing up the IBM BiCMOS technology with at least a starting library of cells. Clearly, proprietary industrial libraries exist in this case.