C. Deliverables

There are no proprietary claims to limit the distribution of deliverables to the ARPA and U.S. communities.

C.1 Layout Generator for Leafcell Layout with Compatibility to Third Layer Metal

  1. The prototype of an automatic, design rule independent layout generator for standard cells using GENIE (Mentor Graphics), suitable for two or three layers of metal will be developed. The layout generator which synthesizes layouts from a structural representation of the cell will be delivered. [YEAR 1]
  2. The modular development of the program, as shown in Fig. 4 will facilitate both user symbollically defined transistor placement and routing and automatic placement and routing. The functionality required to support both methods for layout generation with a referenced set of design rules will be included. The layout generator which synthesizes layouts from a symbolic representation of the cell will be delivered. [YEAR 1]
  3. The creation of the fixed libraries below will lead to refining the algorithms, methods, and improved user control. Revised versions of the above will be released for delivery to the community. [YEAR 2]
  4. A portable tool to support the non-Mentor users which incorporates the place and route algorithms developed above will be delivered. [YEAR 3]

C.2 CMOS Standard Cell Library

C.2.1 HP standard cell library

  1. The additions from the HP library will be redesigned in a conventional fixed transistor implementation form (three layer metal), but supportive of design rule independence. A symbolic description of the cells from the HP library plus a common generator tool will be delivered. [YEAR 1]
  2. The timing results from the characterization of this expanded library for the conventional fixed implementation will be delivered. [Q1 of YEAR 2]
  3. In support of generic macromodeling of the timing for parameterized generator cells (over a reasonable range) required in synthesis, research will focus on how to include the additional variables of stage sizing, fan-in, etc. Characterization methods, models, and data will be developed with the latter two delivered. [YEAR 2]

C.2.2 MSU standard cell library

  1. The MSU expanded library, which includes the ITD cell library as a subset, will be redesigned with design rule independence and parameterized device sizing compatible with the three layer metal policy. A symbolic description of the cells from this MSU/ITD library plus a common generator tool will be delivered. [Q2 of YEAR 2]
  2. The timing results from the characterization of this expanded library for the conventional fixed implementation will be delivered. [Q2 of YEAR 2]
  3. In support of generic macromodeling of the timing for parameterized generator cells (over a reasonable range) required in synthesis, research will focus on how to include the additional variables of stage sizing, fan-in, etc. Characterization methods, models, and data will be developed with the latter two delivered. [Q2 of YEAR 3]

C.2.3 Data Path cell library

  1. MSU will design the logic functions defined in the Hyper/Lager datapath library with design rule independence and parameterized device sizing compatible with the three layer metal policy. A symbolic description of the cells from this library plus a common generator tool will be delivered. [Q3 of YEAR 2]
  2. The timing results from the characterization of this expanded library for the conventional fixed implementation will be delivered. [Q3 of YEAR 2]
  3. In support of generic macromodeling of timing for parameterized generator cells (over a reasonable range) required in synthesis, research will focus on how to include the additional variables of device sizing, etc. Characterization methods, models, and data will be developed with the latter two delivered. [YEAR 2]

C.2.4 BiCMOS standard cell library

  1. The necessary technology related files associated with the MOSIS/IBM BiCMOS technology required for schematic and layout capture, simulation, design rule and electrical rule verification in support of GDT and Checkmate will be created, demonstrated with example designs through MOSIS, and delivered. [Q2 of YEAR 2]
  2. A set of base-line BiCMOS cells compatible with the MOSIS/IBM technology will be delivered. [Q2 of YEAR 2]
  3. High performance BiPolar I/O compatible cells will be designed and delivered. The BiCMOS library of cells will be characterization and with timing modeled. The resulting data will be delivered. [YEAR 3]

C.3 CAD Tool Interfaces

  1. MSU will deliver the necessary interfaces for using the three layer metal library with the Timberwolfe/YACR toolset. [YEAR 1]
  2. MSU will deliver the necessary interfaces for using the three layer metal library with the Mentor toolset. [YEAR 1]
  3. MSU will deliver the necessary interfaces for using the the new three layer metal library with the Cadence toolset. [YEAR 2]
  4. MSU will deliver demonstration datapath designs in the Timberwolfe/YACR, Mentor and Cadence toolsets using the standard cell generator for low power and high performance applications and using the Hyper synthesis interface. [YEAR 3]

C.4 Constraint Driven Design Methodology

  1. .MSU will deliver delay and power macromodels and characterization methods for parameterizable blocks containing variable transistor size components. [YEAR 1]
  2. MSU will deliver a system for delay and power optimization based upon variable transistor size components. The system will utilize optimal path analysis and post-routing layout modification. [YEAR 2]
  3. MSU will demonstrate the delay and power optimization system via several significant datapath intensive designs using the HYPER synthesis system.[YEAR 2 and 3]